Design and analysis of superconducting quantum processors for surface code
ORAL
Abstract
We present an effective numerical method to analyze bus-mediated qubit-qubit couplings and two-qubit-gate speed limits in superconducting quantum processors designed for surface-code quantum error correction. Our hybrid simulation tool, combining finite-element and circuit simulation, enables the investigation of a complex chip layout with limited computational resources. We apply the simulation method to the design of Surface-17 and -49 processors, finding good agreement with the experimental realization of Surface-17.
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Presenters
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Nadia Haider
Netherlands Org Scientific Res
Authors
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Nadia Haider
Netherlands Org Scientific Res
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Marc Beekman
Netherlands Organisation for Applied Scientific Research, Netherlands Organisation for Applied Scientific Research, The Netherlands, QuTech and Netherlands Organisation for Applied Scientific Research, The Netherlands
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Piotr Kaminski
QuTech and Netherlands Organisation for Applied Scientific Research, The Netherlands
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Leonardo DiCarlo
QuTech and Kavli Institute of Nanoscience, Delft University of Technology, The Netherlands, Delft University of Technology