Understanding losses in superconducting circuits fabricated on thin silicon membranes for hybrid quantum systems integration

Dielectric membranes are a promising platform for developing hybrid quantum systems for computing, where superconducting circuits are combined with the long lifetimes of phononic resonators. While there have been advances developing superconducting quantum processors, phononic resonators in thin dielectric membranes can have lifetimes in excess of 1 second, far exceeding the lifetime of any on-chip superconducting circuit. Combining these two technologies requires fabricating superconducting circuits on dielectric membranes. Success depends on understanding and mitigating the losses introduced to the superconducting circuit by the dielectric membranes. We present a study of the loss in superconducting circuits fabricated on silicon membranes using silicon-on-insulator (SOI) chips. We fabricate resonators with various geometries, width of waveguide and impedance, to understand surface and material loss in the SOI system. We present our experimental results and loss analysis including quality factor (Q) measurements at low photon number. SNL is managed and operated by NTESS under DOE NNSA contract DE-NA0003525.