Fabrication parameters for frequency targeting in scalable superconducting quantum processors

The scaling of monolithic superconducting quantum processors based on a repeating unit cell with repeated qubit frequencies presents unique challenges. Qubit frequency targeting must be preserved while incorporating 3D interconnects such as through-silicon vias (TSVs) and airbridges, increasing die form factor to wafer level, and increasing density of resonant components. We present a systematic approach to determine the causes of spread in Al-AlOx-Al Josephson junctions (apart from intrinsic variations in the tunnel barrier) with increased complexity of the quantum plane. Room-temperature resistance measurements are compared for junction arrays fabricated on four variations of substrates, namely bare silicon substrates, bare wafers with TSVs, wafers with pre-patterned superconducting base film, and base-patterned wafers with TSVs. The annealing effect of end-of-line fabrication steps for airbridges is also investigated in an effort to control global drifts in junction resistance