High-fidelity controlled-Z gate with maximal intermediate leakage operating at the speed limit in a superconducting quantum processor

Simple tuneup of high-fidelity two-qubit gates is essential for the scaling of quantum processors. Here, we introduce the sudden variant (SNZ) of the Net Zero scheme realizing high-fidelity, repeatable controlled-Z (CZ) gates by baseband flux control of transmon frequency. SNZ achieves CZ gates at the speed limit of transverse coupling between computational and non-computational states by maximizing intermediate leakage. Beyond speed, the key advantage of SNZ over fast-adiabatic approaches is tuneup simplicity, owing to the regular structure of conditional phase and leakage as a function of two control parameters. We realize SNZ CZ gates in a multi-transmon processor, reaching 99.87±0.27% fidelity with 0.15 ± 0.02% leakage. We use numerical simulations with experimental input parameters to dissect the error budget and compare SNZ to conventional NZ , finding SNZ to outperform. SNZ is compatible with scalable schemes for quantum error correction and adaptable to arbitrary conditional-phase gates useful in NISQ applications.