Device and materials considerations for scaling of spin qubit devices

In this work we discuss the device advantages and challenges of pitch scaling for spin quantum array designs for Si fin based and buried Si/ SiGe channel based technologies. We show with modeling and data how the scaling of qubit parameters important for quantum computing depends on the interplay between device electrostatics, disorder, and quantum confinement. We discuss a need for a virtual compensation in scaled designs, and propose schemes for its implementation. We will also present implications of scaling on a two-qubit-gate fidelity. We discuss that considered template designs and dimensions are achievable in the environment of high volume semiconductor manufacturing.