Using FPGAs to speed up Qubit State Readouts

One of the main challenges of controlling of quantum processors is the need for fast feedback to perform operations such as Quantum Error Correction (QEC) and qubit reset. QEC is a critical technique for the practical feasibility of quantum computers, because qubit gate fidelities are limited compared to their classical counterparts. In order to perform many feedback operations within the lifetime of a qubit, the feedback latency needs to be several orders of magnitude shorter, which rules out software-based signal processing or decision-making. FPGAs are ideal devices to take advantage of hardware speed up and to allow for custom and reconfigurable hardware-based real-time processing. In this workshop we will show how FPGA IP components can enable high fidelity readout of spin and superconducting qubits, using advanced low-latency signal processing and matched filtering techniques. We will also show how qubit state information can be fed to the rest of the qubit control system for feedback operations with a minimal feedback time.