Systematic charge noise characterization of Intel quantum dot devices

Quantum computing promises to tackle exciting and computationally difficult problems. Intel is leveraging 50 years of experience in semiconductor manufacturing to develop silicon-based spin qubit devices. A key challenge in this endeavor is reducing the effect of noise on the spin qubits to an acceptable level. The effects of noise can be reduced by lowering its strength or the sensitivity of the qubits to the noise. For spin qubits, charge noise is an important contributor, limiting coherence and gate fidelity. The impact of charge noise can be mitigated with fabrication changes, so it is important to acquire statistically relevant data in a systematic way. We find that the level of charge noise can vary considerably depending on the configuration of the quantum dot that hosts the spin qubit. Therefore, we measure the noise over large parameter ranges on many quantum dots. Using fast noise measurements, we find two-level systems that increase charge noise excessively. Further, we confirm the linear dependence of charge noise on temperature. Using a cryogenic wafer probing tool that enables efficient 300-mm-wafer-scale measurements at 1.6 K, we can inform fabrication decisions with statistically relevant data. We also highlight the expected impact of noise on system performance.