Enabling transistor scaling with 2D materials

Transistor scaling has been the main driver for a giant boom in productivity and for the development of society and technology as we know them. However, silicon transistor scaling is becoming increasingly difficult and potentially approaches its physical limits. 2D materials could enable this scaling beyond what could be achieved with Si. We will discuss here how a roadmap for 2D materials adoption in transistor scaling can be built and potential technology nodes where these materials can be adopted. Challenges for the technical implementation abound, and we will outline our work to solve them. We will also cover design-technology co-optimization aspects and explain how model calibration can speed-up technological adoption. In this context, we will outline stacked transistor architectures where 2D materials could serve as channel and detail our work for integrated these in flows on 300mm wafers in imec’s CMOS fab.