Exploring single Ti/Pd gate layer MOS devices as diagnostic qubits

The design, fabrication, and characterization of MOS quantum dot devices surface gated with a single Ti/Pd metal layer are presented and discussed. The motivation is to avoid using fragile gate dielectrics that are sometimes seen to break down in multilayer devices and obtain simpler process flows. However, as a tradeoff, we expect reduced electrostatic gate control in single layer design. We observed quantum dots forming in the device channel and gate capacitances consistent with modelling, so that dot positions can be located by triangulation in capacitance modelling. In some cases, non-deliberate dot positions and more dots formed than intended, indicate non-lithographic features in the channel. Nonetheless, the gate capacitance ratios are sufficient to enable charge sensing and persistent feedback mode is used to map charge stability regions over wide gate voltage ranges. Granularity and delamination of the Pd layer in the fine region shown by SEM and AFM, combined with possible Si/SiO₂ interface defects, may account for some of the irregular features in the transport and charge sensing measurements. Overall, these metal single gate layer devices provide ample data for analyzing benefits and costs of this design, and help advancing future implementation of diagnostic qubits.