Mobility limiting factors in Si-MOSFETs fabricated with a full CMOS process

Silicon is one of the leading candidates for future spin- and valley-qubit applications. The performance of these qubits depends mostly on the interface quality, which depends on the fabrication process and the materials used. Here, we study the influence of various gate stacks on the density and mobility of both electrons and holes in Si-MOSFETs fabricated in a full CMOS process. Primarily, the material of the gate stack has the highest impact with peak mobilities ranging from 4’000 to 16’000 cm²/Vs. This is believed to be linked to the strain that the gate stack material exerts on the substrate, therefore influencing the quality of the interface. Various parameters such as the roughness of the interface and background impurity densities were directly extracted from mobility vs density curves, further enhancing the understanding of the mobility limiting factors in these types of devices (Kruithof et al., PRB 43 6642 (1991)). Additionally, from measurements down to millikelvin temperatures we were able to extract parameters such as the effective mass and quantum lifetimes of up to 2 ps. These results show the viability of a full CMOS process for qubit device fabrication.