Fabrication and characterization of compact vacuum gap transmon qubits

The large shunt capacitance of the transmon qubit decreases its sensitivity to charge fluctuations but requires sizeable qubit dimensions. Very large capacitor designs furthermore lower the coupling to parasitic losses localized in material interfaces, an approach that improves coherence times consistently, but lowers the achievable integration density and increases parasitic cross coupling and leakage in superconducting processors. Our goal is the development of a compact low-loss transmon qubit by minimizing the electric field participation ratio of metal-dielectric and dielectric-air interfaces. Several attempts to realize vacuum gap capacitors were already implemented [1, 2], usually relying on an out-of-plane geometry that involved a sacrificial layer before releasing the structure. We utilize silicon membranes to fabricate micro-machined resonators and transmon qubits based on suspended in-plane vacuum capacitors [3] with qubits sizes as low as 20 x 20 μm^2.

[1] K. Cicak et al., Appl. Phys. Lett. 96 (2010)
[2] S. J. Bosman et al., Nat. npj Quantum Inf. 3 (2017)
[3] P. Dieterle et al., Phys. Rev. Applied 6, (2016)