Hardware-Efficient Quantum Error Correction with NV Center

The near-term intermediate-scale quantum (NISQ) era dawns with the demonstration of `quantum supremacy’. In the NISQ era, it is under debate if quantum error correction (QEC) is required. Although QEC is essential towards scalable universal quantum computation, it imposes a prohibitively high overhead for NISQ devices. To reduce the overhead, a hardware-efficient QEC approach has recently been employed and enjoyed experimental success [1]. Applying the same philosophy to our system—a quantum register consisting of one NV electronic spin and neighboring nuclear spins, we have carefully characterized the system and recently identified its dominant decoherence source [2]. Moving forward, we developed a hardware-efficient QEC code for such noise, which requires exponentially less overhead [3], and we are progressing in experiments towards one logical qubit consisting of two physical qubits.

[1] N. Ofek et al., Nature 536, 441 (2016)
[2] M. Chen et al., New J. Phys. 20, 063011 (2018)
[3] D. Layden et al., arXiv: 1903.01046