Considerations for incorporating small logical qubits in digital error correction codes

We introduce a hybrid error correction scheme by considering using traditional error correcting codes (e.g. Surface codes) with small logical qubit architectures, namely, the Very Small Logical Qubit (VSLQ). Previous theoretical work has shown that the VSLQ can achieve a linear scaling improvement factor, with a single qubit T₁ lifetime of 30 µs having a logical lifetime of up to 3 ms, all while using two high-coherence qubits and two lossy qubits or resonators, using passive error correction. In this talk, we consider using small logical qubits such as the VSLQ as part of a broader measurement-based code, and explore potential advantages and challenges from such a hybrid approach. In particular, given that digital error correction normally does not account for qubit leakage error, we explore the complexity that would be introduced in dealing with the corresponding leakage error from VSLQ logical states, as well as other concerns.