Fabrication process and failure analysis for robust quantum dots in silicon

We investigate several yield limiting steps in the fabrication of overlapping aluminum gate quantum dot devices in Si/SiGe. The thin, ~2 nm oxide that grows natively on aluminum and low thermal budget of aluminum devices presents a challenge for fabrication of quantum dot arrays with high yield. Gate-to-gate leakage from pinholing of the aluminum oxide, damage from electrostatic discharge (ESD), low breakdown voltages and gate geometry/morphology all present a significant risk of device failure in the active region. Additionally, dewetting of aluminum and formation of alloys during fabrication of interconnects from the active region of the device to the bond pads can result in failure of electrical signal transmission. We present low-temperature oxidation techniques for a thicker aluminum oxide with breakdown voltages of over 4 volts, reducing the risk of damage due to ESD and gate-to-gate leakage. TEM images of overlapping gate structures identify failure modes stemming from gate geometry/morphology. Finally, we investigate the fabrication of interconnects between the active region and device bond pads to introduce thermal anneals into the fabrication process, prevent damage due to ESD, and to identify the maximum processing temperature at different stages of device fabrication.