Quasi-static C-V Characterization of Traps in Sputtered Bismuth Selenide FET

Bismuth Selenide based devices have gained a lot of attention due to the highly conducting, spin-polarized, topologically protected surface states [1]. They have found a lot of promise in spintronics. Previous works have shown the existence of high charge to spin conversion in sputtered, polycrystalline Bi_xSe_1-x [2-4]. This is attributed to the quantum confinement effect in the individual grains of the film. Characterizations have revealed non-idealities from this material due to charge trapping. In this work, we characterize charge traps in FET devices by quasi-static Capacitance-Voltage measurement. The experimental C-V curve shows a hysteretic behavior which is attributed to oxide and interfacial traps. We use the known charge trapping model to calculate the trap densities for different devices. To further understand the physics of random defects, we simulated the electric field in the FET device by 2D finite difference time domain technique (computational electrodynamics) to analyze the E-field uniformity near a defect edge and along the Bi_xSe_1-x/SiO₂ interface.
[1] Tang et al. npj Quant. Mat. 4, 1 (2019)
[2] DC et al. Nat. Mat. 17, 800 (2018)
[3] Sahu et al. APL 112, 122402 (2018)
[4] Ramaswamy et al. JAP D, 52, 22 (2019)