Breaking the Defect Bottleneck in Halide Perovskite Semiconductors

The physical properties of semiconducting solids depend on the imperfections they contain[1]. Defects come in a few flavours: conductivity-promoting defects create free carriers that enable electronics; killer defects (deep centres) trigger recombination; and charge scattering defects reduce mobility. Our understanding of halide perovskites is limited in comparison to inorganic semiconductors. I will discuss recent progress, from theory and experiment, to identify, characterise and control point defects and defect processes in this family of compounds. I will cover charge compensation mechanisms [2], carrier trapping phenomena[3], the effect of grain boundaries[4], and how this understanding can be applied to engineer defect populations and distributions. The use of `defect tolerance` as a metric to develop and screen post-perovskite materials will be critically addressed.

[1] "Instilling defect tolerance in new compounds" Nature Mater. 16, 964 (2017)
[2] "Self-regulation mechanism for charged point defects in hybrid halide perovskites" Angew. Chem. 54, 1791 (2015)
[3] "H-center and V-center defects in hybrid halide perovskites" ACS Energy Lett. 2, 2713 (2017)
[4] "Accumulation of deep traps at grain boundaries in halide perovskites" ACS Energy Lett. 4, 1321 (2019)