Atomistic Simulations of the Cold Source Field-Effect Transistor for Sub-60 mV/decade Switching

Sub-60 mV/decade subthreshold swing (S) transistors have been the object of considerable research efforts due to their low power dissipations. The cold source field-effect transistor (CSFET) achieves low S by suppressing thermionic emission in the OFF-state through source density-of-states engineering. This device has thus far only been investigated by simulations based on effective mass, k.p, and ballistic approximations. We report the first simulations of CSFETs based on combining the nonequilibrium Green’s functions (NEGF) formalism with the tight-binding (TB) method, thereby capturing the atomistic details of the devices under nonequilibrium conditions. Specifically, we consider gate-all-around Silicon nanowire CSFETs grown in [100], [110], and [111] with diameters ranging from a few Å to a few nm. We find that vacancies and surface roughness have little influence on the performance of the device, which maintains a low S even in the presence of elastic scattering. Finally, we present both n-type and p-type CSFETs, thus substantiating the compatibility of CSFETs with complementary metal–oxide–semiconductor (CMOS) technology.