Towards scalable hole spin qubits in silicon

Since the first proof-of-concept demonstration of a silicon hole spin qubit based on industry-standard CMOS technology [1], our research efforts have focused on acquiring a better understanding of the mechanism for electric-field-driven hole-spin manipulation [2], as well as on the development of spin readout based on rf gate reflectometry [3]. All of these studies were carried out on p-type silicon-nanowire devices with two crossing gates in series. Here we report the first implementation of hole-qubit functionality in a face-to-face gate geometry [4]. This more scalable geometry can be regarded as the elementary building block of a one-dimensional chain of qubits were each qubit on the chain is read through a facing helper quantum dot via the Pauli spin blockade mechanism and rf gate reflectometry [5].

References:
[1] A. Crippa et al., Nature Communications 10, 2776 (2019).
[2] A. Crippa et al., Physical Review Letters 120, 137702 (2018).
[3] S. De Franceschi et al., Technical Digest - IEDM, 13.4.1–13.4.4 (2017).
[4] R. Maurand et al., Nature Communications, 3–8(2016).
[5] B. Voisin et al., Nano Letters 14, 2094–2098 (2014).