3D Integration for Superconducting Qubits

As the field of superconducting quantum computing advances from the few-qubit stage to large-scale fault-tolerant devices, scalability requirements will necessitate the use of standard 3D packaging and integration processes. While the field of 3D integration is well-developed, relatively little work has been performed to determine the compatibility of the associated processes with superconducting qubits. Qubit coherence time could potentially be affected by required process steps or by the proximity of an interposer that could introduce extra sources of charge or flux noise. As a first step towards a large-scale quantum information processor, we have used a flip-chip process to bond a chip with flux qubits to an interposer containing structures for qubit readout and control. We will present data on the effect of the presence of the interposer on qubit coherence time for various qubit-chip-interposer spacings and discuss the implications for integrated multi-qubit devices. This research was funded by the ODNI and IARPA under Air Force Contract No. FA8721-05-C-0002. The views and conclusions contained herein are those of the authors and should not be interpreted as representing the official policies or endorsements, either expressed or implied, of ODNI, IARPA, or the US Government.