Interface investigation of solution processed high-$\kappa $ ZrO$_{\mathrm{2}}$/Si MOS structure by DLTS

The interfacial region is dominating due to the continuous downscaling and integration of high-$k$ oxides in CMOS applications. The accurate characterization of high-$k$ oxides/semiconductor interface has the significant importance towards its usage in memory and thin film devices. The interface traps at the high$-k$/semiconductor interface can be quantified by deep level transient spectroscopy (DLTS) with better accuracy in contrast to capacitance-voltage (CV) and conductance technique. We report the fabrication of high-$k$ ZrO$_{\mathrm{2}}$ films on p-Si substrate by a simple and inexpensive sol-gel spin-coating technique. Further, the ZrO$_{\mathrm{2}}$/Si interface is characterized through DLTS. The flat-band voltage (V$_{\mathrm{FB}})$ and the density of slow interface states (oxide trapped charges) extracted from CV characteristics are 0.37 V and 2x10$^{\mathrm{-11\thinspace }}$C/cm$^{\mathrm{2}}$, respectively. The activation energy, interface state density and capture cross-section quantified by DLTS are E$_{\mathrm{V}}+$0.42 eV, 3.4x10$^{\mathrm{11}}$ eV$^{\mathrm{-1\thinspace }}$cm$^{\mathrm{-2\thinspace }}$and 5.8x10$^{\mathrm{-18\thinspace }}$cm$^{\mathrm{2}}$, respectively. The high quality ZrO$_{\mathrm{2}}$ films own high dielectric constant 15 with low leakage current density might be an appropriate insulating layer in future electronic application. The low value of interface state density and capture cross-section are the indication of high quality interface and the defect present at the interface may not affect the device performance to a great extent. The DLTS study provides a broad understanding about the traps present at the interface of spin-coated ZrO2/Si.