Assessing MOS Interface Quality for Silicon Quantum Dot Device Fabrication

ORAL

Abstract

Defects at the Si-SiO2 interface are capable of trapping electrons and degrading the operation of silicon-based quantum dot devices. To improve device performance, we are working to characterize the interface quality in MOSCAPs and MOSFETs fabricated at NIST by comparing industry standard defect measurements, such as capacitance-voltage (CV), conductance, and mobility, to electron spin resonance (ESR) measurements. This comparison will give insight into the relative role of defects near the band edge and those distributed throughout the gap in degrading device performance. We will discuss our progress toward this goal as well as our latest data and interpretations.

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Authors

  • Ryan Stein

    Joint Quantum Institute, University of Maryland

  • Jin-Sung Kim

    Department of Electrical Engineering, Princeton University

  • S. A. Lyon

    Department of Electrical Engineering, Princeton University, Princeton University, Department of Electrical Engineering, Princeton University, Princeton NJ 08544

  • N. M. Zimmerman

    National Institute of Standards and Technology, Gaithersburg, Maryland 20899, USA, NIST, National Institute of Standards and Technology

  • M. D. Stewart Jr.

    National Institute of Standards and Technology, Gaithersburg, Maryland 20899, USA, National Institute of Standards and Technology