Measurement of thermal boundary conductance at sintered Si-Si interface

Performance of thermoelectric materials is enhanced by reducing thermal conductivity (TC) without appreciably decreasing electrical properties. Recently, nanocrystalline formed by compaction of nanopowder by sintering has been shown to be a promising solution for low TC and high scalability However, little is known about the thermal boundary conductance (TBC) of the grain boundaries, which dominantly affect the TC, because of the difficulty to directly measure the TBC of the local boundaries. We have therefore developed a process to fabricate a highly planer and uniform bonded-interface between Si thin film and Si substrate, which is suitable for measuring the TBC of the interfaces with time-domain thermoreflectance method. We have found that sintering temperature and HF removal of native oxide on the wafers can change the interface structures from uniform to local SiO$_{\mathrm{x}}$ structures, which alter the TBC from 0.1 to 1 GWm$^{-2}$K$^{-1}$ order. Moreover, crystal orientation mismatch can change the TBC by several times. Together with theoretical calculation that relates the TBC and TC of nanocrystalline Si, the measurement results identify the route to reduce the TC less than the state-of-art value.