Impact of a high resistivity transparent (HRT) layer on ultra-thin CdTe devices

Pushing the limits of the absorber layer thickness to submicron levels without compromising the efficiency in CdTe devices is important for several reasons. Reducing the thickness of the CdTe layer can increase the manufacturing speed and lower the material usage, production time, cost and energy needed for production. Thickness fluctuations in these submicron devices can lead to shunting when these fluctuations are comparable to the absorber layer thickness. Introducing a high resistivity transparent (HRT) layer in the device structure can reduce such shunting. We find that the impact of the HRT layer is higher for ultra-thin absorber layers. In this study, the effect of using sputtered ZnO as the HRT layer was investigated for devices with a 0.2 $\mu $m CdTe layer. Our results show a 40{\%} increase in efficiency in the CdTe devices with the HRT layer compared to the devices without the HRT layer. The increase in efficiency is primarily from improved fill factor due to an increase in shunt resistance from 0.15 kohm-cm$^{2}$ to 0.32 kohm-cm$^{2}$. As a result of increased shunt resistance there is an increase in the efficiency as well as a substantial increase in the yield for small dot cells.