Conductance bistability in metal oxide junctions

We are exploring conductance bistability (memory) effects in junctions based on metal oxides, in the context of their possible applications in hybrid CMOS/nanoelectronic (e.g., CMOL [1]) circuits. So far, we have investigated CuO$_{x}$, NbO$_{x}$ and TiO$_{x}$ formed by thermal and plasma oxidation, with or without rapid thermal post-annealing (at 200 to 800$^{\circ}$C for 30 to 300 seconds). Conductance switching effects have been observed for all these materials. Particularly high endurance (over 1000 switching cycles) has been obtained for TiO$_{x}$ junctions plasma oxidized in 15mTorr oxygen and then post-annealed at 700$^{\circ}$C. However, the ON/OFF conductance ratio for these junctions is only about 5, and the sample-to-sample reproducibility is much lower than required for integrated circuit applications. Our plans are to extend our studies to a-Si junctions with one Ag electrode, and multilayer TiO$_{x}$ junctions, with the main goal to improve device reproducibility. The work is supported in part by AFOSR. \\[3pt] [1] K. K. Likharev, ``Hybrid CMOS/Nanoelectronic Circuits,'' accepted for publication in \textit{J. Nanoelectronics and Optoelectronics}, Nov. 2008.