Study on threshold voltages of Pt/SrBi$_{2}$Ta$_{2}$O$_{9}$/Hf-Al-O/Si FeFETs

Complementary ferroelectric-gate field-effect transistors (FeFETs) are attractive for nonvolatile-logic circuit applications after the achievement of long data retention for both $n$- and $p$- channel FeFETs [1, 2]. To demonstrate nonvolatile logic circuits, the threshold voltage should be well controlled. Due to ferroelectricity two threshold voltages $V_{t, left}$ and $V_{t, right}$ can be defined from $I_{d}-V_{g}$ curves as gate voltages at $I_{d}$ =10$^{-6}$A. More than 90 $n$- or $p$-channel Pt/SrBi$_{2}$Ta$_{2}$O$_{9}$/Hf-Al-O/Si FeFETs on a Si chip are studied. The average$ V_{t, left}$ and $V_{t, right}$ are 1.19 and 2.38 V for $n$-channel FeFETs, and -0.76 and 0.40 V for $p$-channel FeFETs, respectively. The standard deviations of $V_{t}$ are 3-5{\%} and 7-8{\%} of the memory window for the $n$- and $p$- channel FeFETs, respectively. $V_{t}$ positions are adjusted by varying the well doping concentrations. Our results indicate possible circuit demonstration. This work was partially supported by NEDO. \newline [1] S. Sakai, et al, \textit{IEEE Electron Devices Lett.}, \textbf{25}, 369(2004). \newline [2] Q.-H. Li, et al , \textit{Appl. Phys. Lett. }\textbf{89}, 222910 (2006).