Silicide Nanowires for Low-Resistance CMOS Transistor Contacts.

Transition metal (TM) silicide nanowires are used as contacts for modern CMOS transistors. (Our smallest wires are $\sim$20 nm thick and $\sim$50 nm wide.) While much research on thick TM silicides was conducted long ago, materials perform differently at the nanoscale. For example, the usual phase transformation sequences (e.g., Ni, Ni2Si, NiSi, NiSi2) for the reaction of thick metal films on Si no longer apply to nanostructures, because the surface and interface energies compete with the bulk energy of a given crystal structure. Therefore, a NiSi film will agglomerate into hemispherical droplets of NiSi by annealing before it reaches the lowest-energy (NiSi2) crystalline structure. These dynamics can be tuned by addition of impurities (such as Pt in Ni). The Si surface preparation is also a more important factor for nanowires than for silicidation of thick TM films. Ni nanowires formed on Si surfaces that were cleaned and amorphized by sputtering with Ar ions have a tendency to form NiSi2 pyramids (``spikes'') even at moderate temperatures ($\sim$400$^{\circ}$C), while similar Ni films formed on atomically clean or hydrogen-terminated Si form uniform NiSi nanowires. Another issue affecting TM silicides is the barrier height between the silicide contact and the silicon transistor. For most TM silicides, the Fermi level of the silicide is aligned with the center of the Si band gap. Therefore, silicide contacts experience Schottky barrier heights of around 0.5 eV for both n-type and p-type Si. The resulting contact resistance becomes a significant term for the overall resistance of modern CMOS transistors. Lowering this contact resistance is an important goal in CMOS research. New materials are under investigation (for example PtSi, which has a barrier height of only 0.3 eV to p-type Si). This talk will describe recent results, with special emphasis on characterization techniques and electrical testing useful for the development of silicide nanowires for CMOS contacts. \newline \newline In collaboration with: P. Grudowski, D. Jawarani, R. Garcia, M.L. Kottke, R.B. Gregory, X.-D. Wang, D. Theodore, P. Fejes, W.J. Taylor, B.Y. Nguyen, C. Capasso, M. Raymond, D. Denning, K. Chang, R. Noble, M. Jahanbani, S. Bolton, P. Crabtree, D. Goedeke, M. Rossow, M. Chowdhury, H. Desjardins, A.Thean.