Semiconductor Nanowires from Materials Science and Device Physics Perspectives

Realization of extremely down-scaled devices gives tough challenges related to technology and materials science. One reason for the concern is that top-down fabricated nano-devices tend to have their properties dominated by process-induced damage, rendering ultra-small devices not so useful. Alternatively, bottom-up fabrication methods may allow dimensions on the scale even below 10 nm, still with superb device properties. I will in this talk describe our research on catalytically induced growth of semiconductor nanowires. Our method uses catalytic gold nanoparticles, allowing tight control of diameter as well as position of where the nanowire grows, with our work completely focused on epitaxially nucleated nanowires in which the nanowire structure can be seen as a coherent, monolithic extension of the crystalline substrate material. One of the most important achievements in this field of research is the realization of atomically abrupt heterostructures within nanowires, in which the material composition can be altered within only one or a few monolayers, thus allowing 1D heterostructure devices to be realized. This has allowed a variety of quantum devices to be realized, such as single-electron transistors, resonant tunneling devices as well as memory storage devices. A related recent field of progress has been the realization of ideally nucleated III-V nanowires on Si substrates, cases where we have also reported functioning III-V heterostructure device structures on Si. All of these device related challenges evolve from an improved understanding of the materials science involved in nucleation of nanowires, in altering of composition of the growing nanowire, in control of the growth direction etc. I will give examples of these materials science issues and will especially dwell on the opportunities to form new kinds of materials, e.g. as 3D complex nanowire structures, resembling nanotrees or nanoforests.