The Technology of Strained Si on Insulator

Scaling of MOSFET dimensions is no longer sufficient to continue performance enhancements that are expected in each subsequent silicon device generation. Improvements in charge carrier mobility are also required to stay on the Moore's curve. To achieve uniform high mobility in Si wafers, it is necessary to introduce a biaxial strain into silicon lattice. This is typically done by epitaxial growth of silicon on a virtual substrate of relaxed SiGe. Thin pseudomorphic layers of Si grow under tensile strain in order to preserve the epitaxy with a larger lattice spacing of the SiGe template. In order to take full advantage of strained Si, the film is transferred to a new substrate in such a way that there is a layer of SiO$_{2}$ between strained Si and the silicon handle wafer. Smart Cut{\texttrademark} technology, which involves wafer bonding and controlled exfoliation from the donor wafer, is the most practical way to accomplish layer transfer while preserving lattice strain. Formation of the virtual substrates is not trivial -- control and minimization of misfit dislocations are critically important. Nevertheless, strained Si on insulator (sSOI) wafers with 200 and 300mm diameter are rapidly becoming an industrial reality. Strain of $\sim $0.8{\%} is induced by growth on relaxed SiGe with 20{\%} Ge content. This can double the electron mobility in n-type transistors. Enhancing p-type devices requires higher strain values or non-standard crystal orientations. The range of strained Si thicknesses from 10-60nm allows fabrication of both fully depleted and partially depleted MOSFETs. Formation of sSOI, its properties and applications will be reviewed.