A Mask-free and Contactless Patterned Plasma Processing Technique for Interdigitated Back Contact Silicon Heterojunction Solar Cells Fabrication
ORAL
Abstract
The interdigitated back contact silicon heterojunction (IBC-SHJ) solar cell currently holds the record efficiency for crystalline silicon PV devices [1]. But such impressive device performance comes at a cost of employing photolithographic patterning steps or a shadow mask to create the interdigitated carrier collection zones required for IBC architectures.
To circumvent the complex fabrication process, we present a novel mask-free and contactless method to form those interdigitated patterns by a PECVD process. It involves using a slotted powered RF electrode, with parallel slits in it, in a CCP-PECVD chamber. By keeping the two electrodes in close proximity, plasma will selectively light only within the slits, thus mimicking the patterns on the electrode [2]. Deploying this patterned plasma process with an NF3/Ar etching gas mixture on a well-designed silicon thin film stack, the interdigitated patterns required for IBC architectures are obtained.
Multiple characterizations are performed along the process flow to give guidance for the processes optimization. J(V) characteristics of the resulting PV devices will be presented, and the importance of an additional step to remove the “damaged” layer on the surface (in the trench) left by the patterned etching process will be discussed.
To circumvent the complex fabrication process, we present a novel mask-free and contactless method to form those interdigitated patterns by a PECVD process. It involves using a slotted powered RF electrode, with parallel slits in it, in a CCP-PECVD chamber. By keeping the two electrodes in close proximity, plasma will selectively light only within the slits, thus mimicking the patterns on the electrode [2]. Deploying this patterned plasma process with an NF3/Ar etching gas mixture on a well-designed silicon thin film stack, the interdigitated patterns required for IBC architectures are obtained.
Multiple characterizations are performed along the process flow to give guidance for the processes optimization. J(V) characteristics of the resulting PV devices will be presented, and the importance of an additional step to remove the “damaged” layer on the surface (in the trench) left by the patterned etching process will be discussed.
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Presenters
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Erik Johnson
LPICM-CNRS, École Polytechnique, Institut Polytechnique de Paris
Authors
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Junkang WANG
LPICM-CNRS, École Polytechnique, Institut Polytechnique de Paris
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Pavel Bulkin
LPICM-CNRS, École Polytechnique, Institut Polytechnique de Paris
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Monalisa Ghosh
LPICM-CNRS, École Polytechnique, Institut Polytechnique de Paris
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Dmitri Daineka
LPICM-CNRS, École Polytechnique, Institut Polytechnique de Paris
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Pere Roca i Cabarrocas
LPICM-CNRS, École Polytechnique, Institut Polytechnique de Paris
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Sergej Filonovich
TotalEnergies OneTech
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José Alvarez
Laboratoire de Génie Electrique et Electronique de Paris, CNRS, CentraleSupélec, Université Paris-Saclay
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Erik Johnson
LPICM-CNRS, École Polytechnique, Institut Polytechnique de Paris