Framework for analyzing scalable ion trap geometries

A utility-scale trapped-ion quantum information processor (QIP) requires millions of qubits with fast operation times and low error rates. Achievable ion number, gate speed, and error rates are all influenced by trap geometry. To understand how design choices affect these parameters, we identify figures of merit (FoM) for comparing different simulated trap geometries useful for actualizing utility-scale QIPs. Decreasing gate time and infidelity necessitates a harmonic trapping potential, high radial trapping frequencies, low heating rates, and a large trap depth. Ease of fabrication is also considered, focusing on the availability of fabrication techniques and common fabrication errors. We apply this framework to three different traps: (1) the surface trap - the most common trap geometry, (2) an enhanced version of surface trap where a grounded wafer is put on top of a surface trap to improve vertical confinement, and (3) a miniaturized 3D Paul trap. The framework concludes that 3D trap geometries offer better field-dependent trapping attributes than the common surface trap. When fabricability is taken into account, the second design is a promising choice for scalability. The framework can be applied to future works in 3D QIP architectures.