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Studying the temperature dependence of the 65 nm CMOS MAPS silicon sensor for future collider tracker upgrades

ORAL

Abstract

Increasing vertex resolution is critical for the next generation of particle collider experiments. The proposal of Silicon Monolithic Active Pixel Sensors (MAPS) in the latest 65 nm process marks a milestone in the evolution of CMOS sensors. The ALICE Collaboration and other contributors are running an ambitious R&D program on the characterization efforts on the first prototype chips. The Digital Pixel Test Structure combines fast digital readout with a large matrix of 32 x 32 pixels. Current research at LBL focuses on the pixel-to-pixel variation of the injection capacitance and thus on energy calibration. A series of tests has therefore been carried out under temperature-controlled conditions. The results presented on fake-hit rate and pixel-to-pixel variations in time-over-threshold and injection capacitance for the sensor chip operating at 15-40°C deepen our understanding of the technology. It also provides important insights into the use of 65nm MAPS sensors at the Electron Ion Collider.

Presenters

  • Jonathan C Witte

    Lawrance Berkeley National Laboratory

Authors

  • Jonathan C Witte

    Lawrance Berkeley National Laboratory

  • Barak Schmookler

    University of California, Riverside