ETROC Project: First full-size and full-function ASIC for the CMS MTD Endcap Timing Layer (ETL) upgrade

The Endcap Timing ReadOut Chip (ETROC) is designed to process MIP-sensitive silicon low-gain avalanche diode (LGAD) signals with time resolution down to about 50 ps per hit to achieve 35 ps per track with two detector layers. Testing of the full-chain ASIC (ETROC1, size 4x4) during the last two years was successfully conducted on a beam telescope with three layers of bump-bonded ETROC1/sensors, resulting in a timing resolution of 42-45 ps per hit. The first full-size (16x16) and full-function prototype ASIC (ETROC2) has been developed on the basis of the pixel analog front-end design of ETROC1, and a switch-cell based network approach is introduced for the pixel readout and global readout design in ETROC2. The time-to-digital-converter (TDC) using uncontrolled delay which has been used for ETROC1 is also implemented on ETROC2. The ETROC2 includes new features such as the on-chip auto discriminator threshold calibration, built-in self-testing capability with digital pattern generation, and the capability to provide a coarse map of delayed hits continuously for every bunch crossing for monitoring or Level 1 triggering purposes. For design verification and testing purposes, the new pixel and global readout have been emulated in FPGA. The status of the initial testing results of ETROC2 is presented.